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Features
* High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture
- 130 Powerful Instructions - Most Single-clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories - 8K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles - 1K Byte Internal SRAM - Programming Lock for Software Security Peripheral Features - Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Three PWM Channels - 8-channel ADC in TQFP and MLF package Six Channels 10-bit Accuracy Two Channels 8-bit Accuracy - 6-channel ADC in PDIP package Four Channels 10-bit Accuracy Two Channels 8-bit Accuracy - Byte-oriented Two-wire Serial Interface - Programmable Serial USART - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages - 23 Programmable I/O Lines - 28-lead PDIP, 32-lead TQFP, and 32-pad MLF Operating Voltages - 2.7 - 5.5V (ATMEGA8L) - 4.5 - 5.5V (ATMEGA8) Speed Grades - 0 - 8 MHz (ATMEGA8L) - 0 - 16 MHz (ATMEGA8) Power Consumption at 4 Mhz, 3V, 25C - Active: 3.6 mA - Idle Mode: 1.0 mA - Power-down Mode: 0.5 A
*
*
8-bit with 8K Bytes In-System Programmable Flash ATMEGA8 ATMEGA8L
Preliminary Summary
*
* * * *
Rev. 2486KS-AVR-08/03
Note: This is a summary document. A complete document is available on our web site at www.atmel.com.
1
Pin Configurations
PDIP
(RESET) PC6 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A)
TQFP Top View
PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
(INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7
1 2 3 4 5 6 7 8
PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK)
32 31 30 29 28 27 26 25
PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2)
(T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4
MLF Top View
(INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK)
2
ATMEGA8(L)
2486KS-AVR-08/03
(T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4
ATMEGA8(L)
Overview
The ATMEGA8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATMEGA8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure 1. Block Diagram
XTAL1 RESET PC0 - PC6 VCC XTAL2 PB0 - PB7
Block Diagram
PORTC DRIVERS/BUFFERS
PORTB DRIVERS/BUFFERS
GND
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
MUX & ADC AGND AREF PROGRAM COUNTER
ADC INTERFACE
TWI
STACK POINTER
TIMERS/ COUNTERS
OSCILLATOR
PROGRAM FLASH
SRAM
INTERNAL OSCILLATOR
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS X
WATCHDOG TIMER
OSCILLATOR
INSTRUCTION DECODER
Y Z
MCU CTRL. & TIMING
CONTROL LINES
ALU
INTERRUPT UNIT
AVR CPU
STATUS REGISTER
EEPROM
PROGRAMMING LOGIC
SPI
USART
+ -
COMP. INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
PD0 - PD7
3
2486KS-AVR-08/03
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATMEGA8 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and MLF packages) where four (six) channels have 10-bit accuracy and two channels have 8-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System SelfProgrammable Flash on a monolithic chip, the Atmel ATMEGA8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATMEGA8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
4
ATMEGA8(L)
2486KS-AVR-08/03
ATMEGA8(L)
Pin Descriptions
VCC GND Port B (PB7..PB0) XTAL1/ XTAL2/TOSC1/TOSC2 Digital supply voltage. Ground. Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in "Alternate Functions of Port B" on page 56 and "System Clock and Clock Options" on page 23. Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 36. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated on page 59. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATMEGA8 as listed on page 61. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 36. Shorter pulses are not guaranteed to generate a reset.
PC6/RESET
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2486KS-AVR-08/03
AVCC
AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC. AREF is the analog reference pin for the A/D Converter. In the TQFP and MLF package, ADC7..6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
AREF ADC7..6 (TQFP and MLF Package Only)
About Code Examples
6
ATMEGA8(L)
2486KS-AVR-08/03
ATMEGA8(L)
Register Summary
Address
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20(1) (0x40)(1) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22)
Name
SREG SPH SPL Reserved GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR
Bit 7
I - SP7 INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SE - -
Bit 6
T - SP6 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SM2 - -
Bit 5
H - SP5 - - TICIE1 ICF1 - TWSTA SM1 - -
Bit 4
S - SP4 - - OCIE1A OCF1A RWWSRE TWSTO SM0 - -
Bit 3
V - SP3 - - OCIE1B OCF1B BLBSET TWWC ISC11 WDRF -
Bit 2
N SP10 SP2 - - TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02
Bit 1
Z SP9 SP1 IVSEL - - - PGERS - ISC01 EXTRF CS01
Bit 0
C SP8 SP0 IVCE - TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00
Page
9 11 11 47, 65 66 70, 100, 120 71, 101, 120 210 167 31, 64 39 70 70 29
Timer/Counter0 (8 Bits) Oscillator Calibration Register - COM1A1 ICNC1 - COM1A0 ICES1 - COM1B1 - - COM1B0 WGM13 ACME FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR10 WGM10 CS10
56, 73, 121, 189 94 98 99 99 99 99 99 99 100 100
Timer/Counter1 - Counter Register High byte Timer/Counter1 - Counter Register Low byte Timer/Counter1 - Output Compare Register A High byte Timer/Counter1 - Output Compare Register A Low byte Timer/Counter1 - Output Compare Register B High byte Timer/Counter1 - Output Compare Register B Low byte Timer/Counter1 - Input Capture Register High byte Timer/Counter1 - Input Capture Register Low byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register - - URSEL URSEL - EEAR7 - - - - UMSEL - EEAR6 - - - - UPM1 - EEAR5 - - WDCE - UPM0 - EEAR4 - USBS - EEAR3 EERIE - EEAR2 EEMWE AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 - EEAR1 EEWE UCPOL EEAR8 EEAR0 EERE TCR2UB WDP0
115 117 117 117 41 154 152 18 18 18 18
EEPROM Data Register
PORTB7 DDB7 PINB7 - - - PORTD7 DDD7 PIND7 SPIF SPIE RXC RXCIE ACD REFS1 ADEN
PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC TXCIE ACBG REFS0 ADSC
PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 - DORD UDRE UDRIE ACO ADLAR ADFR
PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 - MSTR FE RXEN ACI - ADIF
PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 - CPOL DOR TXEN ACIE MUX3 ADIE
PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 - CPHA PE UCSZ2 ACIC MUX2 ADPS2
PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 - SPR1 U2X RXB8 ACIS1 MUX1 ADPS1
PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0
63 63 63 63 63 63 63 63 63 128 128 126 149 150 151 154 190 201 203 204 204 169
SPI Data Register
USART I/O Data Register
USART Baud Rate Register Low byte
ADC Data Register High byte ADC Data Register Low byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
170
7
2486KS-AVR-08/03
Register Summary (Continued)
Address
0x01 (0x21) 0x00 (0x20)
Name
TWSR TWBR
Bit 7
TWS7
Bit 6
TWS6
Bit 5
TWS5
Bit 4
TWS4
Bit 3
TWS3
Bit 2
-
Bit 1
TWPS1
Bit 0
TWPS0
Page
169 167
Two-wire Serial Interface Bit Rate Register
Notes:
1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
8
ATMEGA8(L)
2486KS-AVR-08/03
ATMEGA8(L)
Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr
1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1
PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1
R1:R0 (Rd x Rr) <<
BRANCH INSTRUCTIONS
9
2486KS-AVR-08/03
Instruction Set Summary (Continued)
Mnemonics
BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Rd, Z Rd, Z+ k k Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr
Operands
Description
Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG
Operation
if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I 0 S1 S0 V1 V0 T1
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T
#Clocks
1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATA TRANSFER INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
10
ATMEGA8(L)
2486KS-AVR-08/03
ATMEGA8(L)
Instruction Set Summary (Continued)
Mnemonics
CLT SEH CLH
Operands
Clear T in SREG
Description
T0 H1 H0 Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
Operation
T H H
Flags
#Clocks
1 1 1
MCU CONTROL INSTRUCTIONS NOP SLEEP WDR
No Operation Sleep Watchdog Reset
(see specific descr. for Sleep function) (see specific descr. for WDR/timer)
None None None
1 1 1
11
2486KS-AVR-08/03
Ordering Information
Speed (MHz) 8 Power Supply 2.7 - 5.5 Ordering Code ATMEGA8L-8AC ATMEGA8L-8PC ATMEGA8L-8MC ATMEGA8L-8AI ATMEGA8L-8PI ATMEGA8L-8MI 16 4.5 - 5.5 ATMEGA8-16AC ATMEGA8-16PC ATMEGA8-16MC ATMEGA8-16AI ATMEGA8-16PI ATMEGA8-16MI Note: Package 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
Package Type 32A 28P3 32M1-A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF)
12
ATMEGA8(L)
2486KS-AVR-08/03
ATMEGA8(L)
Packaging Information
32A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.00 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B
R
13
2486KS-AVR-08/03
28P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
B2
A1
(4 PLACES)
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.508 34.544 7.620 7.112 0.381 1.143 0.762 3.175 0.203 - NOM - - - - - - - - - - - MAX 4.5724 - 34.798 8.255 7.493 0.533 1.397 1.143 3.429 0.356 10.160 Note 1 Note 1 NOTE
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 B2 L C eB e
2.540 TYP
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P3 REV. B
R
14
ATMEGA8(L)
2486KS-AVR-08/03
ATMEGA8(L)
32M1-A
D D1
1 2 3
0
Pin 1 ID E1 E
SIDE VIEW
TOP VIEW
A2
A3 A1 A
0.08 C
P D2
Pin 1 ID
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.80 - - NOM 0.90 0.02 0.65 0.20 REF 0.18 0.23 5.00 BSC 4.75 BSC 2.95 3.10 5.00 BSC 4.75BSC 2.95 3.10 0.50 BSC 0.30 - - 0.40 - - 0.50 0.60 12o 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTE
1 2 3
P
A A1 E2 A2 A3 b D D1
b
e
L
D2 E
BOTTOM VIEW
E1 E2 e L
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
P
0
01/15/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. C
R
15
2486KS-AVR-08/03
Erratas
ATMEGA8 Rev. D, E, F, and G
The revision letter in this section refers to the revision of the ATMEGA8 device. * CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 1. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 When the internal RC Oscillator is used as the main clock source, it is possible to run the Timer/Counter2 asynchronously by connecting a 32 KHz Oscillator between XTAL1/TOSC1 and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed. Problem fix/Workaround Use external capacitors in the range of 20 - 36 pF on XTAL1/TOSC1 and XTAL2/TOSC2. This will be fixed in ATMEGA8 Rev. G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is selected as main clock source. For ATMEGA8 Rev. G, CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Customers who want compatibility between Rev. G and older revisions, must ensure that CKOPT is unprogrammed (CKOPT = 1).
16
ATMEGA8(L)
2486KS-AVR-08/03
ATMEGA8(L)
Data Sheet Change Log for ATMEGA8
Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
This document contains a log on the changes made to the data sheet for ATMEGA8.
All page numbers refers to this document. 1 Updated TWI Chapter. More details regarding use of the TWI Power-down operation and using the TWI as Master with low TWBRR values are added into the data sheet. Added the note at the end of the "Bit Rate Generator Unit" on page 166. Added the description at the end of "Address Match Unit" on page 166. 2 Updated Description of OSCCAL Calibration Byte. In the data sheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of "Oscillator Calibration Register - OSCCAL" on page 29 and "Calibration Byte" on page 221. 3 Added Some Preliminary Test Limits and Characterization Data. Removed some of the TBD's in the following tables and pages: Table 3 on page 24, Table 15 on page 36, Table 16 on page 40, Table 17 on page 42, "DC Characteristics TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted)" on page 237, Table 99 on page 239, and Table 102 on page 241. 4 Updated Programming Figures. Figure 104 on page 222 and Figure 112 on page 232 are updated to also reflect that AVCC must be connected during Programming mode. 5 Added a Description on how to Enter Parallel Programming Mode if RESET Pin is Disabled or if External Oscillators are Selected. Added a note in section "Enter Programming Mode" on page 224
Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
All page numbers refers to this document. 1 Updated Typical Start-up Times. The following tables has been updated: Table 5, "Start-up Times for the Crystal Oscillator Clock Selection," on page 26, Table 6, "Start-up Times for the Low-frequency Crystal Oscillator Clock Selection," on page 26, Table 8, "Start-up Times for the External RC Oscillator Clock Selection," on page 27, and Table 12, "Start-up Times for the External Clock Selection," on page 30. 2 Added "ATMEGA8 Typical Characteristics - Preliminary Data" on page 244.
17
2486KS-AVR-08/03
Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
All page numbers refers to this document. 1 Updated Some Preliminary Test Limits and Characterization Data The following tables have been updated: Table 15, "Reset Characteristics," on page 36, Table 16, "Internal Voltage Reference Characteristics," on page 40, DC Characteristics on page 237, Table , "ADC Characteristics - Preliminary Data," on page 243. 2 Changes in External Clock Frequency Added the description at the end of "External Clock" on page 30. Added period changing data in Table 99, "External Clock Drive," on page 239. 3 Updated TWI Chapter More details regarding use of the TWI bit rate prescaler and a Table 65, "TWI Bit Rate Prescaler," on page 169.
Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
All page numbers refers to this document. 1 2 3 Changes in "Digital Input Enable and Sleep Modes" on page 53. Addition of OCS2 in "MOSI/OC2 - Port B, Bit 3" on page 57. The following tables has been updated: Table 51, "CPOL and CPHA Functionality," on page 129, Table 59, "UCPOL Bit Settings," on page 154, Table 72, "Analog Comparator Multiplexed Input (1) ," on page 191, Table 73, "ADC Conversion Time," on page 196, Table 75, "Input Channel Selections," on page 202, and Table 84, "Explanation of Different Variables used in Figure 103 and the Mapping to the Z-pointer," on page 218. 5 6 Changes in "Reading the Calibration Byte" on page 230. Corrected Errors in Cross References.
Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02 Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02 Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
All page numbers refers to this document. 1 Updated Table 103, "ADC Characteristics," on page 243.
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
1. Added errata for Rev D, E, and F on page 16.
18
ATMEGA8(L)
2486KS-AVR-08/03
ATMEGA8(L)
Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
1. Improved the description of "Asynchronous Timer Clock - clkASY" on page 24. 2. Removed reference to the "Multipurpose Oscillator" application note and the "32 kHz Crystal Oscillator" application note, which do not exist. 3. Corrected OCn waveforms in Figure 38 on page 88. 4. Various minor Timer 1 corrections. 5. Various minor TWI corrections. 6. Added note under "Filling the Temporary Buffer (Page Loading)" on page 213 about writing to the EEPROM during an SPM Page load. 7. Removed ADHSM completely. 8. Added section "EEPROM Write during Power-down Sleep Mode" on page 21. 9. Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of "Port B (PB7..PB0) XTAL1/ XTAL2/TOSC1/TOSC2" on page 5. 10. Improved the table under "SPI Timing Characteristics" on page 241 and removed the table under "SPI Serial Programming Characteristics" on page 236. 11. Corrected PC6 in "Alternate Functions of Port C" on page 59. 12. Corrected PB6 and PB7 in "Alternate Functions of Port B" on page 56. 13. Corrected 230.4 Mbps to 230.4 kbps under "Examples of Baud Rate Setting" on page 155. 14. Added information about PWM symmetry for Timer 2 in "Phase Correct PWM Mode" on page 111. 15. Added thick lines around accessible registers in Figure 76 on page 165. 16. Changed "will be ignored" to "must be written to zero" for unused Z-pointer bits under "Performing a Page Write" on page 213. 17. Added note for RSTDISBL Fuse in Table 87 on page 220. 18. Updated drawings in "Packaging Information" on page 13.
Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
1. Updated VBOT values in Table 15 on page 36. 2. Updated "ADC Characteristics - Preliminary Data" on page 242. 3. Updated "ATMEGA8 Typical Characteristics - Preliminary Data" on page 243. 4. Updated "Erratas" on page 16.
19
2486KS-AVR-08/03
Atmel Corporation
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